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Piezoelectric Tunnel FET With a Steep Slope

2020-07-02

Author(s): Long, YX (Long, Yuxiong); Huang, JZ (Huang, Jun Z.); Huang, QQ (Huang, Qianqian); Xu, N (Xu, Nuo); Jiang, XW (Jiang, Xiangwei); Niu, ZC (Niu, Zhi-Chuan); Huang, R (Huang, Ru); Li, SS (Li, Shu-Shen)

Source: IEEE ELECTRON DEVICE LETTERS Volume: 41 Issue: 6 Pages: 948-951 DOI: 10.1109/LED.2020.2988412 Published: JUN 2020

Abstract: A design of n-type InAs piezoelectric tunnel FETs (PE-TFETs), which is worth further experimental verification, is proposedfor steep sub-thresholdslope and studied using TCAD simulations. Piezoelectric layers (PE-layer) are inserted in gate stacks to induce dynamic compressive strain and to modulate the band gap during switching. The non-equilibriumGreen's function (NEGF) approach with strained 8-band k center dot p Hamiltonian is used to investigate the PE-TFETs performance. Our results suggest that PE-TFETs are compressively strained perpendicular to the transport direction at OFF state, while PE-TFETs feel no strain at ON state. This compressive strain enlarges the channel band gap and meanwhile reduces the tunneling energy window, which greatly suppresses OFF current. In this work, the n type InAs PE-TFETs achieve 50 times lower OFF current than conventional TFETs, and the minimum SS of PE-TFETs is 48 mV/dec with 0.5 V supply voltage. Moreover, the proposed design is helpful to suppress the ambipolar current.

Accession Number: WOS:000541155300039

ISSN: 0741-3106

eISSN: 1558-0563

Full Text: https://ieeexplore.ieee.org/document/9069277



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